There are a number of competing pressures in the fabrication of semiconductor devices. It is important that devices are fabricated accurately so as to either avoid device failure or to reduce the number of devices on a wafer that fail. It is also important that devices meet manufacturing specifications to ensure that the devices operate correctly even if they do not fail. There is also a requirement of reproducibility so that devices fabricated from different wafers all meet manufacturing specifications. Even if an acceptable level of reproducibility is in fact met, there can also be a perceived reproducibility in which designers of devices require comfort that manufacturing specifications can always be met and are not being met merely as a matter of luck.
There is also the competing pressure of throughput which requires semiconductor device manufacturing tools to operate quickly in order to provide a required throughput of devices. However, speed of fabrication tends to militate against the reproducibility and accuracy of device fabrication.
A common step in the fabrication of semiconductor devices is etching a feature into a layer of a wafer. The depth of the feature can often be a critical factor in the correct operation or failure of the device or otherwise a key manufacturing specification.
One mechanism by which people have tried to ensure that features with the correct depth are etched is to provide an etch stop layer in the wafer prior to etching. The presence of an etch stop layer provides a way to prevent the feature from being etched deeper than the etch stop layer, but requires a more complicated wafer structure to start with and is therefore complex and costly. Also, in some devices an etch stop layer cannot be used as it would interfere with the correct operation of the device. Further, it can be necessary to etch into a wafer substrate which does not include an etch stop layer.
Various optical techniques have also been used to control etch processes. For example in a gate manufacturing process, optical emission spectroscopy can be used to determine when a layer of polycrystalline silicon has been etched through. The emission spectrum changes when the gate oxide layer is exposed and begins to etch and so the gate oxide layer can be detected. However, again this requires the presence of a special layer effectively acting as an etch stop indicator in the wafer. Further some etching of the gate oxide layer needs to occur in order to generate the change in the emission spectrum and so the depth of the etch through the polysilicon layer cannot be carefully controlled.
Another method which does not provide sufficiently accurate etch depth control is the use of interferometry based techniques. A single step etch is used to etch the feature and an interferometric end point (IEP) device is used to measure the relative change in depth of the feature that has been etched into the wafer. When the desired relative change in etch depth is measured, the etching is stopped. However, high etch rate processes cannot stop etching immediately and in a reproducible manner and so there tends to be a significant variation in the actual depth etched. The lack of control of etch depth and lack of reproducibility can lead to device failure or to failure to meet manufacturing specifications or to wafer-to-wafer variations that do not meet device designers requirements.
There is therefore a need for a simple, reproducible method for accurately controlling etch depth while still providing sufficient processing throughput.